View ISL76321ARZ_9078681.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fn7803 rev 2.00 page 1 of 14 may 1, 2015 fn7803 rev 2.00 may 1, 2015 isl76321 16-bit long-reach video automotive grade serdes with bi-directi onal side-channel datasheet the isl76321 is a serializer/deserializer of lvcmos parallel video data. the video data presented to the serializer on the parallel lvcmos bus is serialized into a high-speed differential signal. this differential signal is converted back to parallel video at the remote end by the deserializer. it also transports auxiliary data bi-directionally over the same link during the video vertical retrace interval. i 2 c bus mastering allows the placement of external slave devices on the remote side of the link. an i 2 c controller can be placed on either side of the link allowing bidirectional i 2 c communication through the link to the external devices on the othe r side. both chips can be fully configured from a single controller or independently by local controllers. related literature ? isl34341 data sheet ?wsvga 24-bit long-reach video serdes with bi-directional side-channel? features ? 16-bit rgb transport over a single differential pair ? 6mhz to 50mhz pixel clock rates ? aec-q100 qualified component ? bi-directional auxiliary data transport without extra bandwidth and over the same differential pair ? hot-plugging with automatic resynchronization every hsync ?i 2 c bus mastering to the remote side of the link with a controller on either the serializer or deserializer ? selectable clock edge for parallel data output ? dc-balanced with industry standard 8b/10b line code allows ac-coupling, providing immunity against ground shifts ? 16 programmable settings each for transmitter amplitude boost and pre-emphasis and receiver equalization, allow for longer cable lengths and higher data rates ? slew rate control and spread spectrum capability on outputs reduce the potential for emi ? same device for serializer and deserializer simplifies inventory applications ? video entertainment systems ?remote cameras seriop serion 27nf 27nf seriop serion 27nf 27nf isl76321 deserializer pclk_in rgb ref_clk pclk_out vsync hsync de video_tx i2ca0 i2ca1 ref_res test_en gnd_cr gnd_p gnd_an gnd_tx gnd_cdr gnd_io rstb/pdb vdd_io vdd_cr vdd_p vdd_an vdd_tx vdd_cdr 3.16k 3.3v 1.8v vdd_io 16 video target isl76321 serializer rgb pclk_in vsync hsync de video_tx i2ca0 i2ca1 ref_res test_en gnd_cr gnd_p gnd_an gnd_tx gnd_cdr gnd_io rstb/pdb vdd_io vdd_cr vdd_p vdd_an vdd_tx vdd_cdr 3.3v 1.8v vdd_io vdd_io 16 video source 3.16k figure 1. typical application
isl76321 fn7803 rev 2.00 page 2 of 14 may 1, 2015 block diagram 8b/10b x20 rgb v/h/ d e seriop serion sda 16 3 pclk_ out x20 tx rx mux demux cdr vcm generator i 2 c scl pre- emphasis eq tdm ram video_tx (hi) pclk_in (ref_clk when video_tx is lo)
isl76321 fn7803 rev 2.00 page 3 of 14 may 1, 2015 pin configuration isl76321 (48 ld qfn) top view gnd_io rgba7 rgba6 rgba5 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 rgba4 rgba3 rgba2 rgba1 rgba0 pclk_out vdd_io gnd_io gnd_cr vdd_cr dataen hsync vsync vhsyncpol video_tx pclk_in gnd_p vdd_p scl sda vdd_cdr gnd_cdr vdd_tx seriop serion gnd_tx vdd_an gnd_an ref_res master i2ca0 i2ca1 vdd_io rgbc0 rgbc1 rgbc2 rgbc3 rgbc4 rgbc5 rgbc6 rgbc7 status test_en rstb/pdb pin descriptions pin number pin name description serializer de serializer 47, 46 45, 44 43, 42 41, 40 9, 8 7, 6 5, 4 3, 2 rgba7, rgba6 rgba5, rgba4 rgba3, rgba2 rgba1, rgba0 rgbc7, rgbc6 rgbc5, rgbc4 rgbc3, rgbc2 rgbc1, rgbc0 parallel video data lvcmos inputs with hy steresis parallel video data lvcmos outputs 16 hsync horizontal (line) sync lvcmos input with hysteresis horizontal (line) sync lvcmos output 17 vsync vertical (frame) sync lvcmos input with hysteresis vertical (frame) sync lvcmos output 15 dataen video data enable lvcmos input with hysteresis video data enable lvcmos output 20 pclk_in pixel clock lvcmos input p ll reference clock lvcmos input 39 pclk_out default; not used recovered clock lvcmos output 33, 32 seriop, serion high-speed differential serial i/o high speed differential serial i/o
isl76321 fn7803 rev 2.00 page 4 of 14 may 1, 2015 18 vhsyncpol cmos input for hsync and vsync polarity 1: hsync & vsync active low 0: hsync & vsync active high 19 video_tx cmos input for video flow direction 1: video serializer 0: video deserializer 24, 23 sda, scl ( note 1 )i 2 c interface pins (i 2 c data, i 2 c clk), weak internal pull-up 25, 26 i2ca[1:0] ( note 1 )i 2 c device address 27 master i 2 c master mode 1: master 0: slave 12 rstb/pdb cmos input for reset and power-down. for normal operation, this pin should be driven high. when this pin is taken low, the device will be reset. if this pin stays low, the device will be in pd mode. 10 status cmos output for receiver status: 1: valid 8b/10b data received 0: no valid data detected note: serializer and deserializer switch roles during side-channel reverse traffic 28 ref_res analog bias setting resistor connection; use 3.16k 1% to ground 21 gnd_p ( note 2 )pll ground 37, 48 gnd_io ( note 2 ) digital (parallel and control) ground 35 gnd_cdr ( note 2 ) analog (serial) data recovery ground 31 gnd_tx ( note 2 ) analog (serial) output ground 29 gnd_an ( note 2 ) analog bias ground 13 gnd_cr ( note 2 ) core logic ground 14 vdd_cr core logic vdd 34 vdd_tx analog (serial) output vdd 30 vdd_an analog bias vdd 36 vdd_cdr analog (serial) data recovery vdd 1, 38 vdd_io ( note 1 ) digital (parallel and control) vdd 22 vdd_p pll vdd 11 test_en must be connected to ground exposed pad pad must be connected to ground, not an electrical connection notes: 1. pins with the same name are internally connected together. howe ver, this connection must not be used for connecting together external components or features. 2. the various differently-named ground pins are internally weakly connected. they must be tied together externally. the differe nt names are provided to assist in minimizing the current loops involved in bypassing the associated supply vdd pins. in particular, for esd testing, they should be considered a common connection. pin descriptions (continued) pin number pin name description serializer de serializer
isl76321 fn7803 rev 2.00 page 5 of 14 may 1, 2015 ordering information part number ( notes 3 , 4 , 5 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL76321ARZ isl76321 arz -40 to +105 48 ld qfn l48.7x7c notes: 3. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 4. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl76321 . for more information on msl please see techbrief tb363 .
isl76321 fn7803 rev 2.00 page 6 of 14 may 1, 2015 absolute maximum rating s thermal information supply voltage vdd_p to gnd_ p , vdd_tx to gnd _tx , vdd_io to gnd_io . . -0.5v to 4.6v vdd_cdr to gnd_cdr, vdd_cr to gnd_cr . . . . . . . . . . . . . . . . -0.5v to 2.5v between any pair of gnd_p, gnd_tx, gnd_io, gnd_cdr, gnd_cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1v to 0.1v 3.3v tolerant lvttl/lvcmos input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vdd_io +0.3v differential input voltage . . . . . . . . . . . . . . . . . . . . .-0.3v to vdd_io + 0.3v differential output current . . . . . . . . . . . . . . . . . . . . short circuit protected lvttl/lvcmos outputs. . . . . . . . . . . . . . . . . . . . . . . short circuit protected esd rating human body model (tested per jesd22-a114e) all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kv seriop/n (all vdd connected, all gnd connected) . . . . . . . . . . . . . . . . . . . . . . 8kv machine model (tested per jesd-a115-a) . . . . . . . . . . . . . . . . . . . . 200v charge device model (tested per aec-q100-011-b) . . . . . . . . . . . 2000v latch-up (tested per jesd-78b; class2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja ? jc (c/w) qfn package ( notes 6 , 7 ) . . . . . . . . . . . . . . 32 3.7 maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mw maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions operating temperature range . . . . . . . . . . . . . . . . . . . . . .-40c to +105c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 7. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. boldface limits apply over the operating temperature range, -40c to +105c. parameter symbol conditions min ( note 10 )typ max ( note 10 )units power supply voltage vdd_cdr, vdd_cr 1.7 1.8 1.9 v vdd_tx, vdd_p, vdd_an, vdd_io 3.0 3.3 3.6 v serializer power supply currents total 1.8v supply current pclk_in = 45mhz 62 80 ma total 3.3v supply current ( note 8 )40 52 ma deserializer power supply currents total 1.8v supply current pclk_in = 45mhz 66 76 ma total 3.3v supply current ( note 8 )50 63 ma power-down supply current total 1.8v power-down supply current rstb = gnd 10 ma total 3.3v power-down supply current 0.5 ma parallel interface high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input leakage current i in -1 0.01 1 a high level output voltage v oh i oh = -4.0ma, vdd_io = 3.0v 2.6 v low level output voltage v ol i ol = 4.0ma, vdd_io = 3.6v 0.4 v output short circuit current i osc 35 ma
isl76321 fn7803 rev 2.00 page 7 of 14 may 1, 2015 output rise and fall times t or /t of slew rate control set to min c l = 8pf 1ns slew rate control set to max, c l = 8pf 4ns serializer parallel interface pclk_in frequency f in 650mhz pclk_in duty cycle t idc 40 50 60 % parallel input setup time t is 3.5 ns parallel input hold time t ih 1.0 ns deserializer parallel interface pclk_out frequency f out 650mhz pclk_out duty cycle t odc 50 % pclk_out period jitter (rms) t oj clock randomizer off 0.5 %t pclk pclk_out spread width t osprd clock randomizer on 20 %t pclk pclk_out to parallel data outputs (includes sync and de pins) t dv relative to pclk_out, ( note 9 ) -1.0 5.5 ns deserializer output latency t cpd inherent in the design 4 9 14 pclk deserializer reference clock (r ef_clk is fed into pclk_in) ref_clk lock time t pll 100 s ref_clk to pclk_out maximum frequency offset pclk_out is the recovered clock 1500 5000 ppm high-speed transmitter hs differential output voltage, transition bit vod tr txcn = 0x00 650 800 900 mv p-p txcn = 0x0f 900 mv p-p txcn = 0xf0 1100 mv p-p txcn = 0xff 1300 mv p-p hs differential output voltage, non-transition bit vod ntr txcn = 0x00 650 800 900 mv p-p txcn = 0x0f 900 mv p-p txcn = 0xf0 430 mv p-p txcn = 0xff 600 mv p-p hs generated output common mode voltage v ocm 2.35 v hs common mode serializer-deserializer voltage difference ? v cm 10 20 mv hs differential output impedance r out 80 100 120 hs output latency t lpd inherent in the design 4 7 10 pclk hs output rise and fall times t r/ t f 20% to 80% 150 ps hs differential skew t skew <10 ps hs output random jitter t rj pclk_in = 45mhz 6 ps rms hs output deterministic jitter t dj pclk_in = 45mhz 25 ps p-p electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter symbol conditions min ( note 10 )typ max ( note 10 )units
isl76321 fn7803 rev 2.00 page 8 of 14 may 1, 2015 high speed receiver hs differential input voltage v id 75 mv p-p hs generated input common mode voltage v icm 2.32 v hs differential input impedance r in 80 100 120 ? hs maximum jitter tolerance 0.50 ui p-p i 2 c i 2 c clock rate (on scl) f i2c 100 400 khz i 2 c clock pulse width (hi or lo) 1.3 s i 2 c clock low to data out valid 01 s i 2 c start/stop setup/hold time 0.6 s i 2 c data in setup time 100 ns i 2 c data in hold time 100 ns i 2 c data out hold time 100 ms notes: 8. iddio is nominally 50a and not includ ed in this total as it is dominate d by the loading of the parallel pins. 9. this parameter is the output data skew from the invalid edge of pclk_out. the setup and hold time provided to a system is dep endent on the pclk frequency and is calculated as follows: 0.5 * f in - t dv. . 10. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter symbol conditions min ( note 10 )typ max ( note 10 )units
isl76321 fn7803 rev 2.00 page 9 of 14 may 1, 2015 timing diagrams figure 2. vod vs tx setting vod transition bit vod non-transition bit bit boundary bit boundary bit boundary vcm txp txn voltage tx setting 0x0f 0xf0 0xff 0x00 figure 3. parallel video input timing 1/f in t idc t is t ih t ih t is serializer mode pclk_in (rising edge default) valid data valid data valid data data ignored data ignored rgba[7:0], rgbc[7:0] hsync or vsync (hvsyncpol = ?0?) dataen (active ?1? default)
isl76321 fn7803 rev 2.00 page 10 of 14 may 1, 2015 applications detailed description and operation a pair of isl76321 serdes transports 16-bit parallel video for the isl76321 along with auxili ary data over a single 100 differential cable either to a di splay or from a camera. auxiliary data is transferred in both directions every video frame. this feature can be used for remote configuration and telemetry. the benefits include lower emi, lower costs, greater reliability and space savings. the same device ca n be configured to be either a serializer or deserializer by setting one pin (video_tx), simplifying inventory. rgba/c, vsync, hsync, and dataen pins are inputs in serializer mode and outputs in deserializer mode. the video data presented to the serializer on the parallel lvcmos bus is serialized into a high-speed differential signal. this differential signal is converted back to parallel video at the remote end by the deserializer. the side channel data (auxiliary data) is transferred between the serdes pair during the first two lines of the vertical video blanking interval. when the side-channel is enabled, which is the default, there will be a number of pclk cycles uncertainty from frame-to-frame. this should not cause sync problems with most displays, as this occurs during the vertical front porch of the blanking period. when properly configured, the serdes link supports end-to-end transport with fewer than one error in 10 10 bits. differential signals and termination the isl76321 serializes the 16-bit parallel data plus 3 sync signals at 20x the pclk_in frequency. the extra 2 bits per word come from the 8b/10b encoding scheme which helps create the highest quality serial link. the high bit rate of the differential serial data requires special care in the layout of traces on pcbs, in the choice and assembly of connectors, and in the cables themselves. pcb traces need to be adjacent, matched in length and drawn to result in a differential 100 controlled impedance. for best emi performance, the cable should be low loss and have a differential 100 impedance. the maximum cable length for a functioning link is dependent on the pclk_i n frequency, the cable loss and impedance, as well as the pre-emphasis and equalization settings. functioning links of 25 meters are often possible at the maximum frequency. seriop and serion pins incorporate internal differential termination of the serial signal lines. serio pin ac-coupling ac-coupling minimizes the effect s of dc common mode voltage difference and local power supply variations between two serdes. the serializer outputs dc balanced 8b/10b line code, which allows ac-coupling. the ac-coupling capacitor on serio pins must be 27nf on the serializer board and 27nf on the deserializer board. the value of the ac-coupling capacitor is very critical since a value too small will attenuate the high-speed sign al at a low clock rate. a value too big will slow down the turn around time for the side-channel. it is an advantage to have the pair of capacitors as closely matched as possible. receiver reference clock (ref_clk) the reference clock (ref_clk) for the pll is fed into pclk_in pin. ref_clk is used to recover the clock from the high-speed serial stream. ref_clk is very se nsitive to any instability. the following conditions must be met at all times after power is applied to the deserializer, or else the deserializer may need a manual reset: ? vdd must be applied and stable ? ref_clk frequency must be within the limits specified ? ref_clk amplitude must be stable a simple 3.3v cmos crystal oscillator can be used for ref_clk power supply sequencing the 3.3v supply must be higher than the 1.8v supply at all times, including during power-up and power-down. to meet this requirement, the 3.3v supply must be powered up before the 1.8v supply. for the deserializer, ref_clk must not be applied before the device is fully powered up. applying ref_clk before power-up figure 4. parallel video output timing deserializer mode pclk_out (rising edge default) 1/fout t odc t or t of t dv t dv valid data valid data valid data previous data held rgba[7:0], rgbc[7:0] hsync or vsync ( hvsyncpol = ?0?) dataen (active ?1? default)
isl76321 fn7803 rev 2.00 page 11 of 14 may 1, 2015 may require the deserializer to be manually reset. a 10ms delay after the 1.8v supply is powered up guarantees normal operation. power supply bypassing and layout the serializer and de serializer functions rely on the stable functioning of plls locked to local reference sources or locked to an incoming signal. it is impo rtant that the various supplies (vdd_p, vdd_an, vdd_cdr, vdd_tx) be well bypassed over a wide range of frequencies, from below the typical loop bandwidth of the pll to approaching the signal bit rate of the serial data. a combination of different values of capacitors from 1000pf to 5f or more with low esr characteristics is generally required. the parallel lvcmos vdd_io supply is inherently less sensitive, but since the rgb and sync/datae n signals can all swing on the same clock edge, the current in these pins, and the corresponding gnd pins, can undergo substantial current flow changes. once again, a combin ation of different values of capacitors over a wide range, with low esr characteristics, is desirable. a set of arrangements of this type is shown in figure 5 , where each supply is bypassed with a ferrite-bead-based choke, and a range of capacitors. a ?choke? is preferable to an ?inductor? in this application, since a high-q inductor will be likely to cause one or more resonances with the shunt capacitors, potentially causing problems at or near those frequencies, while a ?lossy? choke will reflect a high impedance over a wide frequency range. the higher value capacitor, in particular, needs to be chosen carefully, with special care rega rding its esr. very good results can be obtained with multilayer ceramic capacitors (available from many suppliers) and generally in small outlines (such as the 1210 outline suggested in the schematic shown in figure 5 ), which provide good bypass capabilities down to a few m at 1mhz to 2mhz. other capacitor technologies may also be suitable (perhaps niobium oxide), but ?classic? electrolytic capacitors frequently have esr values of above 1 , that nullify any decoupling effect above the 1khz to 10khz frequency range. capacitors of 0.1f offer low impedance in the 10mhz to 20mhz region, and 1000pf capacitors in the 100mhz to 200mhz region. in general, one of the lower value capacitors should be used at each supply pin on the ic. figure 5 shows the grounding of the various capacitors to the pin corresponding to the supply pin. although all the ground supplies ar e tied together, the pcb layout should be arranged to emulate th is arrangement (at least for the smaller value (high frequency) capacitors), as much as possible. i 2 c interface the i 2 c interface allows access to internal registers used to configure the serdes and to obtain status information. a serializer must be assigned a different addr ess than its deserializer counterpart if the side channel is used. the upper 5 bits are permanently set to 011 11 and the lower 2 bits determined by pins as follows: thus, 4 serdes can reside on the same bus. by convention, when all address pins are tied low, the device address is referred to as 0x78. scl and sda are open drain to allow multiple devices to share the bus. if not used, scl and sda should be tied to vdd_io. side channel interface the side channel is a mechanism for transferring data between the two chips on each end of the link. this data is transferred during video blanking so none of the video bandwidth is used. it has three basic uses: ? remote serdes configuration ? data exchanges between two processors ?master mode i 2 c commands to remote slaves this interface allows the user to initialize registers, control and monitor both serdes chips from a single microcontroller which can reside on either side of the serial link. this feature is used to automatically transport the remote side serdes chip?s status back to a local register. the side channel needs to be enabled (the default) for this to work. in the case where there is a microcontroller on each side of the of the link, data can be buffered and exchanged between the two. up to 224 bytes can be sent in each direction during each vsync active period. 01111i2ca1i2ca0r/w figure 5. power supply bypassing 10f 10f 10f 10f 10f 10f 120 120 120 120 120 120 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f
isl76321 fn7803 rev 2.00 page 12 of 14 may 1, 2015 master mode this is a mode activated by strapping the master pin to a ?1? on the isl76321 on the remote side of the link from the microcontroller. this is a virtual extension of the i 2 c interface across the link that allows the local processor to read and write slave devices connected to the remote side serdes i 2 c bus. no additional wires or components ar e needed other than the serial link. the i 2 c commands and data are transferred during video blanking causing no interruptions in the video data. in master mode, the data is transported across the link by the side channel so the maximum throughput achi evable would be the same. the scl and sda frequency is adjust able through the programming of a register. if a serdes chip is configured as a master it is no longer available for communication by a local microcontroller. it is assumed that the serdes is the only master. exposed pad while it is not a required electrical connection, it is recommended that the exposed pad on the bottom of the package be soldered to the circuit board. this will ensure that the full power dissipation of the package can be utilized. the pad should be connected to ground and not left floating. for best thermal conductivity, 16 vias should connect the footprint for the exposed pad on the circuit board to the ground plane. this connection is not required for basic operation of the chip. figure 6. layout for the exposed pad copper pad vias 16x
fn7803 rev 2.00 page 13 of 14 may 1, 2015 isl76321 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2011-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change may 1, 2015 fn7803.2 updated aec q100 by adding a dash - now reading aec-q100 in features on page 1 ?absolute maximum ratings? on page 6 - changed charge device model from charge device model (tested per jesd22-c101c) to (tested per aec-q100-011-b) december 23, 2013 fn7803.1 page 13 - 2nd line of the disclaimer changed from: "intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted" to: "intersil automotive qualified products are manu factured, assembled and tested utilizing ts16949 quality systems as noted" january 31, 2011 fn7803.0 initial release.
isl76321 fn7803 rev 2.00 page 14 of 14 may 1, 2015 package outline drawing l48.7x7c 48 lead quad flat no-lead plastic package (punch qfn) rev 0, 1/08 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, tol erance : decimal 0.05, body tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.18mm and 0.28mm fr om the terminal tip. frame dimension b applies to the met allized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to jesd-mo220. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view bottom view c0.400x45x 11 all around 1 e b l 0.450 (0 . 1 25 ) package outline (4x) 0.15 index area 6 pin 1 4 pin #1 index area 6 r0.200 max all around 0.100 c a b (4x) y 0.050 c 0.100 c a b 0.080 c 1 48 0.100 c typ. r0.115 typ. r0.200 r0.200 exposed pad area a b c plane seating ( a l l a r o u n d ) z 48 1 0.025 0.02 0.85 0.65 (4x) x 1 48 (4x) (48x 0.20) (48x 0.23) (48x 0.60) (44x 0.50) 7.00 4.10 (48x 0.40 0.1mm) 0.23 (44x 0.50) 7.00 ref 4.10 ref 6.75 7.00 7.00 6.75 7.00 6.75 0.19~ 0.245 tolerance 0.1 base metal thickness 0.203mm. detail "z" detail "y"

▲Up To Search▲

Price & Availability of ISL76321ARZ

	To Download ISL76321ARZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .